Test methods and ICs for high-speed serdes

This session addresses test challenges associated with high speed I/Os including adaptive equalization, die-to-die link interoperability, and PLL characterization. Adaptive equalization (e.g., decision feedback equalization (DFE)) has become important as data rates approach 6 Gbps or higher, and test and characterization are challenging because DFE is embedded in a complex feedback loop. Embedded I/Os in a multiple chip modules pose unique challenges because there are no observable test pins available. PLL circuits are widely used in SERDES, and characterizing its bandwidth and peaking using an on-chip circuit simplifies the data capture and analysis.