A 32-bit 64-word 9-read, 7-write ported, noise and process variation-tolerant and wide-voltage-range-operative register file using 130 nm technology

Author

Ikeda, Yuuichirou ; Sumita, Masaya

Author_Institution

Matsushita Electr. Ind. Co. Ltd., Kyoto, Japan

fYear

2004

Firstpage

164

Lastpage

167

Abstract

We have developed a 32-bit, 64-word 9-read, 7-write ported register file for a processor based on 130 nm process technology. This register file has several circuits for improving noise and process variation tolerance, such as self-timing control circuits and crosstalk reduction circuits. Body bias voltage control can also be employed. These circuits and techniques confer tolerance to noise and process variation, allowing the register file to be operated over a wide voltage range from 0.6 V to 2.2 V.

Keywords

CMOS memory circuits; crosstalk; memory architecture; microprocessor chips; nanoelectronics; timing; 0.6 to 2.2 V; 130 nm; 32 bit; CMOS process; Shmoo plot; body bias voltage control; crosstalk reduction circuits; multiport memory; noise variation-tolerant register file; ported register file; process variation-tolerant register file; register file floorplan; replica memory cell; self-timing control circuits; single-bit lines; wide-voltage-range-operative register file; write-accurate circuits; Circuit noise; Crosstalk; Delay effects; Inverters; MOS devices; Registers; Semiconductor device noise; Threshold voltage; Timing; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-8637-X

Type

conf

DOI

10.1109/APASIC.2004.1349438

Filename

1349438