A reconfigurable public-key cryptography coprocessor

Author

Zeng, Xiaopng ; Chen, Chao ; Zhang, Qianling

Author_Institution

ASIC & Syst. State Key Lab., Fudan Univ., Shanghai, China

fYear

2004

Firstpage

172

Lastpage

175

Abstract

A new RSA/ECC coprocessor with the characteristic of reconfiguration is proposed in this paper, which can meet the requirements of both GF(p) and GF(2\´") fields and perform the prevalent cryptographies such as RSA and ECC. The coprocessor has the merit of reconfigurable architecture, and it can perform the modular multiplication from 32-bit to 512-bit without any modification to its hardware. Based on 0.35 μm CMOS technology, area of the coprocessor is about 45K gates, and system frequency can up to 100MHz, the 512-bit modular multiplication achieve 190kbps and the 233-bit ECC encryption rate of 50kbps.

Keywords

CMOS digital integrated circuits; Galois fields; application specific integrated circuits; coprocessors; field programmable gate arrays; firmware; instruction sets; public key cryptography; reconfigurable architectures; 32 bit; 512 bit; ASIC; CMOS technology; FPGA; GF(2^m) fields; GF(p) fields; RSA/ECC coprocessor; information security; instruction set design; microcode instruction set; modular multiplication; public-key cryptography coprocessor; reconfigurable architecture; reconfigurable coprocessor; Acceleration; Arithmetic; CMOS technology; Coprocessors; Decoding; Elliptic curve cryptography; Elliptic curves; Hardware; Public key cryptography; Read only memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-8637-X

Type

conf

DOI

10.1109/APASIC.2004.1349440

Filename

1349440