Interconnect delay aware RTL Verilog bus architecture generation for an SoC

As feature size is scaled down to the submicron level, interconnect delay in the design of a high-speed System-on-a-Chip (SoC) becomes a major concern. This concern is especially acute for on-chip buses. In this paper we describe a methodology to generate a custom bus architecture using accurate estimations of interconnect delay. To improve bus delay accuracy, the bus Verilog register-transfer level (RTL) specification was altered based on interconnect delay estimations. Interconnect delay information is provided from an estimated chip layout. The delay estimates for the on-chip buses are used early in the design phase with a corresponding impact on system correctness and performance. As an example of interconnect delay aware bus generation, we compare three different General Global Bus Architecture (GGBA) configurations, showing that certain system blocks (the memory controllers) need to be modified based on interconnect delay estimation. The three different GGBA configurations are evaluated through the simulation of an orthogonal frequency division multiplexing (OFDM) wireless transmitter application. The impact of accurate interconnect delay estimation is shown through a 35.3% reduction in execution time between a worst-case bus delay configuration (GGBA III) and an accurate interconnect delay aware GGBA configuration (GGBA II).