An MPEG-2 video decoder DSP architecture

Author

Rudberg, Mikael Karlsson ; Wanhammar, Lars

Author_Institution

Dept. of Electr. Eng., Linkoping Univ., Sweden

fYear

1996

Firstpage

199

Lastpage

202

Abstract

The MPEG-2 video standard is a generic international standard for applications such as digital storage media, television broadcasting, and multimedia. A novel MPEG-2 video decoder architecture is presented. The use of dedicated processing elements in an asynchronous communication structure gives a high degree of modularity. A semi-static scheduling scheme is used to keep the resource utilization high

Keywords

CMOS digital integrated circuits; asynchronous transfer mode; code standards; decoding; digital signal processing chips; discrete cosine transforms; telecommunication standards; transform coding; video coding; CMOS standard cell library; DCT; DSP architecture; MPEG-2 video decoder; MPEG-2 video standard; asynchronous communication structure; dedicated processing elements; digital storage media; generic international standard; multimedia; resource utilization; semistatic scheduling; television broadcasting; Computer architecture; Decoding; Digital signal processing; Discrete cosine transforms; Hardware; Processor scheduling; Random access memory; Software algorithms; TV; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital Signal Processing Workshop Proceedings, 1996., IEEE

Conference_Location

Loen

Print_ISBN

0-7803-3629-1

Type

conf

DOI

10.1109/DSPWS.1996.555495

Filename

555495