A parallel flop synchronizer for bridging asynchronous clock domains

Inter-domain communications on a chip require a synchronizer to resolve the timing problems between an input and a clock of a destination. This paper presents a parallel flop synchronizer and its interface circuit for transferring asynchronous data between clock domains. The proposed scheme uses a bank of independent two-flops in parallel and supports a two-phase handshake protocol. Compared to the conventional two-flop synchronizer, performance analysis shows that the proposed synchronization can reduce latency up to one and a half of clock cycles while retaining its safety to a tolerable level.