DocumentCode
1700987
Title
A parallel-pipelined processor for fast fourier transform
Author
Tze-Yun Sung ; Chich-Sin Chen
Author_Institution
Chung Hua University
fYear
2004
Firstpage
193
Lastpage
196
Abstract
In this paper, we proposed a novel VLSI FFT processor based on parallel-pipelined constant geometry algorithm (PCGA). This processor provides constant geometry for each stage of FFT, data reordering is not needed any more. Especially, the PCGA FFT processor increases throughput with increasing number of input points, and sufficiently exploits the advantage of parallel-pipelines computation for digital signal processing applications.
Keywords
Computational geometry; Computer architecture; Concurrent computing; Fast Fourier transforms; Hardware; Interleaved codes; Process design; Random access memory; Read-write memory; Signal processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on
Conference_Location
Fukuoka, Japan
Print_ISBN
0-7803-8637-X
Type
conf
DOI
10.1109/APASIC.2004.1349447
Filename
1349447
Link To Document