DocumentCode
1701024
Title
A novel implementation of cost-effective parallel-pipelined 8x8 DCT processor
Author
Sung, Tze-Yun ; Sung, Yi-Hsun
Author_Institution
Chung Hua University
fYear
2004
Firstpage
201
Lastpage
204
Keywords
Arithmetic; CMOS technology; Clocks; Computer architecture; Discrete cosine transforms; Discrete transforms; Image coding; Kernel; Power dissipation; Signal generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on
Print_ISBN
0-7803-8637-X
Type
conf
DOI
10.1109/APASIC.2004.1349449
Filename
1349449
Link To Document