Implementation of a bit-level super-systolic FIR filter

High performance computation on a large array of cells has been an important feature of the systolic array. To achieve higher degree of concurrency, it is desirable to make cells of a systolic array themselves a systolic array as well. The structure of a systolic array with its cells consisting of another systolic array is to be called super-systolic array. This paper proposes a bit-level super-systolic FIR filter with an FPGA-based bit-serial semi-systolic multiplier which twists on the shift and add multiplier by positioning upper and lower half of the serial multiplier side by side physically in floorplanning, instead of linearly. The proposed design is better suited to FPGA implementation than bit-level super-systolic FIR filter with a bit-serial systolic multiplier in each cell in terms of hardware complexity, P&R and performance.