FPGA implementation of an all-digital T/2-spaced QPSK receiver with Farrow interpolation timing synchronizer and recursive Costas loop

This paper describes a FPGA implementation of an all-digital QPSK receiver. The non-data-aided early-late delay (NDA-ELD) synchronization scheme based on T/2-Spaced Farrow Interpolation is employed to find the best symbol timing, and a second-order recursive digital Costas loop is used to track the carrier phase. Hardware design is performed using Verilog HDL and realized in FPGA. The whole design can be efficiently fitted into an Altera EP1S25F780C5 FPGA chip, with only 4% utilization of logic elements, 2% utilization of memory bits, and 65% utilization of DSP block elements. The hardware test results under a symbol rate of 1M symbols/sec are well-matched to both the Matlab algorithmic and Quartus II timing simulations.