DocumentCode
1701391
Title
Modeling and simulation for ESD protection circuit design and optimization
Author
Iyer, Natarajan Mahadeva ; Vassilev, Vesselin ; Thijs, Steven ; Groeseneken, Guido
Author_Institution
Silicon Process. & Device Technol. Div., IMEC, Leuven, Belgium
fYear
2004
Abstract
An overview of the application of modeling and simulation methodologies for ESD protection circuit design optimization is presented. This methodology will reduce the development cycle time and costs and consists of a device compact model definition valid under ESD conditions and circuit level optimization of the protection circuits. This enables to extract information on the ESD robustness of the product at pre-silicon phase and could lead to first-time-right product designs.
Keywords
circuit optimisation; circuit simulation; electrostatic discharge; ESD protection circuit; circuit design; circuit level optimization; circuit modeling; circuit simulation; development cycle cost; development cycle time; pre-silicon phase; Circuit simulation; Circuit synthesis; Cost function; Data mining; Design optimization; Electrostatic discharge; Optimization methods; Product design; Protection; Robustness;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Electronics, 2004. ICSE 2004. IEEE International Conference on
Print_ISBN
0-7803-8658-2
Type
conf
DOI
10.1109/SMELEC.2004.1620823
Filename
1620823
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