Title :
Direct access test scheme for IP core protection
Author :
Fan, Yu-Cheng ; Yang, Hsueh-Yen ; Tsao, Hen-Wai
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
In this paper, we propose a novel direct access test scheme for intellectual property (IP) protection. The principles of new watermarking IP protection procedures depend on current IP-based design flow. The core concept is embedding a watermark generator and a test circuit into the IP core at the behavior design level. This method adopts the direct access test scheme. The ownership right is proven during the direct access test process. The watermark does not need to be designed case-by-case according to different IPs. On real designs, our approaches have low hardware overhead, tracking cost, processing time cost, and probability of coincidence. This scheme can protect the soft IP core at various design levels. It is still easy to detect the ownership rights of the IP provider after the chip has been manufactured and packaged Experimental results have demonstrated that the proposed direct access test scheme-based watermarking approaches are indeed practical. The IP provider will be able to trace a company that has engaged in the unauthorized reselling of copies of the IP.
Keywords :
design for testability; system-on-chip; watermarking; IP core protection; IP reusable rule; behavior design level; binary sequence; direct access test scheme; embedded watermark generator; inverter gates; low hardware overhead; low probability of coincidence; low processing time cost; low tracking cost; ownership rights; parallel input serial output registers; soft IP core; system on chip; Automata; Circuit testing; Constraint optimization; Costs; Design methodology; Design optimization; Intellectual property; Protection; System-on-a-chip; Watermarking;
Conference_Titel :
Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on
Print_ISBN :
0-7803-8637-X
DOI :
10.1109/APASIC.2004.1349467