DocumentCode
1701553
Title
False aggressors pruning using path sensitization and logic implications
Author
Lee, Hyungwoo ; Kim, Juho
Author_Institution
Dept. of Comput. Sci., Sogang Univ., Seoul, South Korea
fYear
2004
Firstpage
278
Lastpage
281
Abstract
Coupled line switching can contribute to a large portion of the delay as well as the functionality of a circuit. In order to fix a crosstalk noise in noise analysis, it is necessary an additional design cost. Therefore, aggressor nodes that cannot affect victim node have to pruning. In this paper, we present an efficient false aggressor pruning algorithm with functional correlation. Path sensitization algorithm and logic implication approach that use functional information to identify false coupling interaction between coupled lines. Our experimental results show an average of 5.4% aggressor pruning and 14.6% delay reduction due to pruning.
Keywords
cellular arrays; circuit layout CAD; combinational circuits; crosstalk; logic CAD; timing; aggressor classification; combination circuits; coupled capacitance; coupled line switching; delay reduction; false aggressors pruning; functional correlation; logic implication approach; path sensitization; standard-cell library; Capacitance; Circuit noise; Clocks; Coupling circuits; Crosstalk; Delay; Logic; Switches; Switching circuits; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on
Print_ISBN
0-7803-8637-X
Type
conf
DOI
10.1109/APASIC.2004.1349471
Filename
1349471
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