Output-bit selection with X-avoidance using multiple counters for test-response compaction

Output-bit selection is a recently proposed test-response compaction approach that can effectively deal with aliasing, unknown-value, and low-diagnosis problems. This approach has been implemented using a single counter and a multiplexer without considering unknown values. Also, such an implementation may require the application of a pattern multiple times in order to observe all selected responses. In this paper, we present a multiple-counter-based architecture with a new selection algorithm that can avoid most unknown-values yet achieve high compaction ratio. The remaining small number of unknowns can then be dealt with using some simple masking logic. Experiments on IWLS´05 circuits show that even with 16% unknown responses, all unknown values can be handled with 88.92%~93.21% response-volume reduction still achieved and only a moderate increase in test-application time.