A 3.1-10.6 GHz CMOS cascaded two-stage distributed amplifier for ultra-wideband application

Author

Chen, Kuan-Hung ; Wang, Chomg-Kuang

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2004

Firstpage

296

Lastpage

299

Abstract

In this paper, a CMOS cascaded two-stage distributed amplifier for ultra-wideband (UWB) application is presented. The circuit using two-stage cascaded topology achieves better gain-bandwidth product performance than conventional CMOS distributed amplifiers. The simulated gain is 18dB with ±1dB gain flatness over 3.1∼10.6 GHz bands. Input and output are matched to 50Ω, and the return losses of input and output are below -10dB and -9dB respectively. The power dissipation is 54mW with 1.8V power supply. The circuit was fabricated in 0.18-μm 1P6M RF CMOS process.

Keywords

CMOS analogue integrated circuits; MMIC amplifiers; S-parameters; cascade networks; distributed amplifiers; field effect MMIC; integrated circuit noise; low-power electronics; wideband amplifiers; 1.8 V; 18 dB; 3.1 to 10.6 GHz; 54 mW; CMOS distributed amplifier; S-parameters; cascaded two-stage distributed amplifier; gain-bandwidth product performance; high gain property; noise figure; power dissipation; two-stage cascaded topology; ultrawideband application; Bandwidth; CMOS process; CMOS technology; Circuits; Cutoff frequency; Distributed amplifiers; Radio frequency; Topology; Transmission lines; Ultra wideband technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-8637-X

Type

conf

DOI

10.1109/APASIC.2004.1349477

Filename

1349477