47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking

Author

Saito, Mitsuko ; Sugimori, Yasufumi ; Kohama, Yoshinori ; Yoshida, Yoichi ; Miura, Noriyuki ; Ishikuro, Hiroki ; Kuroda, Tadahiro

Author_Institution

Keio Univ., Yokohama, Japan

fYear

2009

Firstpage

449

Lastpage

452

Abstract

An inductive-coupling programmable bus is developed for NAND flash memory access in Solid State Drive (SSD). A channel arrangement scheme using 3 coils enables random access for memory read and memory write. Transmission power is reduced by 47% compared to a previous design with 2 coils and a shield. A coil layout style, namely XY coil, allows the coils covered by logic interconnections, resulting in area reduction by 91%. Relayed data transmission at 1.6 Gb/s and BER<10^-12 is achieved.

Keywords

NAND circuits; flash memories; integrated circuit interconnections; logic gates; NAND flash memory stacking; area reduction; channel arrangement scheme; inductive-coupling programmable bus; logic interconnections; memory read; memory write; power reduction; random access; relayed data transmission; solid state drive; transmission power; Coils; Data communication; Logic; Read-write memory; Relays; Solid state circuits; Stacking;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2009. CICC '09. IEEE

Conference_Location

San Jose, CA

Print_ISBN

978-1-4244-4071-9

Electronic_ISBN

978-1-4244-4073-3

Type

conf

DOI

10.1109/CICC.2009.5280819

Filename

5280819