Towards a general purpose mixed-signal instrumentation layer in the die stack of a 3D-SIC

This paper proposes the use of an instrumentation layer in the die stack of a 3D-stacked IC for making precision on-chip measurements for silicon debug, device ramp-up and calibration purposes. As the instrumentation die communicates with the IC stack via the 1149.4 test bus, it can be removed from the stack to reduce the overall cost of the IC when in full production mode. Design effort on a full suite of analog instruments can be performed once and shared between different IC implementations, thereby reducing development costs. The initial focus of this work is on the development of a set of instruments that will be used to characterize the through-silicon via(s) (TSVs) of a 3D-CMOS process. Circuit details related to the design of a 3D-SIC using the Tezzaron 2-Tier 130 nm CMOS process are outlined.