• DocumentCode
    1702026
  • Title

    Digital wireline and PLL techniques

  • Author

    Wei, Gu-Yeon ; Momtaz, Afshin

  • Author_Institution
    Harvard University, USA
  • fYear
    2009
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    Trends in deeply-scaled CMOS technology motivate designers to carefully consider using more digital circuitry and digital control techniques for high-speed wireline transceivers and related building blocks. This session presents recent developments in the design and analysis of various digital approaches.
  • Keywords
    CMOS digital integrated circuits; CMOS technology; Digital control; Phase locked loops; Transceivers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 2009. CICC '09. IEEE
  • Conference_Location
    San Jose, CA, USA
  • Print_ISBN
    978-1-4244-4071-9
  • Electronic_ISBN
    978-1-4244-4073-3
  • Type

    conf

  • DOI
    10.1109/CICC.2009.5280829
  • Filename
    5280829
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1702026