Design and implementation of a routing switch for on-chip interconnection networks

One of the major challenges of system-on-chip (SoC) designs is the communication architecture between heterogeneous components possessing different characteristics. Most of the communication architectures for current SoC designs are based on buses. However, the bus architecture has its inherent limitations. A packet-switched network which delivers messages between communicating components has been proposed as the solution for next-generation SoC Such on-chip interconnection networks provide a chip-level communication infrastructure. In this paper, we present the design and implementation of a routing switch which is the key component for on-chip interconnection networks with mesh or torus topologies. In our design, separate buffers and lookahead routing are employed to effectively solve the blocking problems of packets in buffers. Our simulations show that the on-chip interconnection network with such routing switches outperforms that with conventional switches. We have implemented our switch in 0.25μm technology with cell-based design. An initial version of the implementation of the switch can be run at approximately 100MHz.