A 1-Gflop triangular pseudo-systolic processor

Modern signal processing often requires arithmetically intensive algorithms. The complexity of such algorithms and their development of `batch processing´ solutions does not, in general, provide the bandwidth or convenience required for processing signals in real-time at rates greater than a few hertz; a different approach is needed. J.G. McWhirter and T.J. Shepherd (1987) proposed a systolic architecture which provided the basis for an efficient `flow-through´ processing technique and much effort has since been devoted to the development of suitable algorithms. In particular, signal processing techniques which make use of a least-squares optimisation are often used in signal processing strategies. It was shown by McWhirter and Shepherd that the QR algorithm, used for least-squares optimisation, could be expressed in a form suited to a triangular systolic array. However, the number of systolic nodes and hence processors, in an array capable of optimising a problem with 81 unknowns, for example, would be 3321; such an array would be large and expensive. An intermediate and economically attractive alternative is to use substantially fewer processors emulating the same flow-through architecture whilst providing sufficient bandwidth; a `pseudo-systolic´ solution. Using this approach a group of nodes would share a processor