A programmable-logic based multiprocessor engine for real-time vision preprocessing

Real-time vision is central to many embedded applications (e.g. vehicle guidance). It is a computationally intensive task well beyond current general purpose computing platforms such as PCs and workstations. Thus, most real time vision systems need special high performance computing platforms, commonly provided in the form of parallel processing engines or dedicated hardware. The proposed architecture uses new generations of re-programmable logic devices and modularised hardware, thereby gaining the performance advantage of hard-wired logic with the flexibility and associated economies of programmable systems. The architecture takes the form of an extensive processing hierarchy consisting of a set of tightly coupled parallel processors, each processing a portion of the image using a classic pipeline arrangement. A programmable image splitting (and reconstruction) engine feeds this array and offers the potential of further enhancing the performance of the engines by restructuring the pixel distribution (bit-shuffling) so as to match the requirements of the executing algorithms. The physical implementation will be based on a modularised bus system together with EPLD processing devices. The authors report on the predicted performance of low level vision functions running on this architecture