Title :
A dynamically reconfigurable IP for data-intensive applications
Author :
Miyamoto, Naoto ; Karnan, L. ; Kotani, Koji ; Ohmi, Tadahiro
Author_Institution :
Graduate Sch. of Eng., Tohoku Univ., Miyagi, Japan
Abstract :
In this paper, we introduce a report on designing an ASIC which includes a dynamically reconfigurable IP that can change composition within a clock cycle. Empirical design TAT evaluations were made and the results showed that a data-intensive processor equipped with this IP can be designed in 4 weeks.
Keywords :
circuit CAD; integrated circuit design; microprocessor chips; reconfigurable architectures; system-on-chip; ASIC design; FFT-based processors; SoC; data-intensive applications; dynamically reconfigurable IP; empirical design TAT evaluations; hardware configuration; interface protocols; time-to-market; Application specific integrated circuits; Circuit synthesis; Clocks; Consumer electronics; Design engineering; Fast Fourier transforms; Hardware; Intellectual property; Manufacturing; Time to market;
Conference_Titel :
Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on
Print_ISBN :
0-7803-8637-X
DOI :
10.1109/APASIC.2004.1349512
