An SRAM reliability test macro for fully-automated statistical measurements of Vmin degradation

Author

Kim, Tae-Hyoung ; Zhang, Wei ; Kim, Chris H.

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN, USA

fYear

2009

Firstpage

231

Lastpage

234

Abstract

An SRAM reliability test macro is designed in a 1.2 V, 65 nm CMOS process for statistical measurements of V_min degradation. An automated test program efficiently collects statistical V_min data and reduces test time. The proposed test structure enables V_min degradation measurements for different SRAM failure modes such as the SNM-limited case and the access-time-limited case. The impact of voltage stress on the time to cell data flip was measured.

Keywords

CMOS memory circuits; SRAM chips; automatic testing; integrated circuit reliability; integrated circuit testing; macros; statistical analysis; voltage measurement; CMOS process; SNM-limited case; SRAM reliability test macro design; access-time-limited case; automated test program; cell data flip; failure modes; fully-automated statistical measurement; minimum operating voltage degradation; size 65 nm; voltage 1.2 V; voltage stress impact; Automatic testing; CMOS process; Degradation; Random access memory; Stress measurement; Time measurement; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2009. CICC '09. IEEE

Conference_Location

San Jose, CA

Print_ISBN

978-1-4244-4071-9

Electronic_ISBN

978-1-4244-4073-3

Type

conf

DOI

10.1109/CICC.2009.5280846

Filename

5280846