DocumentCode
1702628
Title
A 0.46ps RJrms 5GHz wideband LC PLL for multi-protocol 10Gb/s SerDes
Author
Rao, Chethan ; Wang, Alvin ; Desai, Shaishav
Author_Institution
Prism Circuits, Santa Clara, CA, USA
fYear
2009
Firstpage
239
Lastpage
242
Abstract
A 2.3 to 5 GHz LC PLL is implemented in 65 nm standard CMOS for 0.6 to 10 Gb/s SerDes applications. The LC VCO is measured to have 67% coarse tuning range and worst-case hold range of 9.6%. The rms random jitter (RJrms) on the TX output with a clock pattern is measured to be 460 fs at 5 GHz and 548 fs at 3.125 GHz. The total power dissipated from the 1.8 V, 1.0 V supplies is 29 mW at 5 GHz.
Keywords
CMOS integrated circuits; MMIC oscillators; phase locked loops; voltage-controlled oscillators; CMOS technology; MMIC oscillators; SerDes; bit rate 10 Gbit/s; frequency 2.3 GHz to 5 GHz; hold range; phase locked loops; power 29 mW; tuning range; voltage 1.0 V; voltage 1.8 V; voltage-controlled oscillators; Clocks; Jitter; Phase locked loops; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2009. CICC '09. IEEE
Conference_Location
San Jose, CA
Print_ISBN
978-1-4244-4071-9
Electronic_ISBN
978-1-4244-4073-3
Type
conf
DOI
10.1109/CICC.2009.5280848
Filename
5280848
Link To Document