A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC

Author

Song, Minyoung ; Kwak, Young-Ho ; Ahn, Sunghoon ; Kim, Wooseok ; Park, ByeongHa ; Kim, Chulwoo

Author_Institution

Korea Univ., Seoul, South Korea

fYear

2009

Firstpage

243

Lastpage

246

Abstract

An ADPLL with a piecewise linear calibrated hierarchical TDC is proposed to achieve a wide range of operation and a CPPLL is cascaded to filter out 1/f noise. A phase selectable divider is also proposed to divide the clock frequency while keeping the relative phase difference of output same as that of input. The cascaded hybrid PLL fabricated in 65 nm CMOS process burns 17 mW and occupies 0.4 mm². The measured jitters are 1.1 ns_pp and 223.6 ps_rms, respectively with a multiplication factor of 1,024.

Keywords

CMOS integrated circuits; cascade networks; charge pump circuits; digital phase locked loops; piecewise linear techniques; 1/f noise; ADPLL; CMOS process; CPPLL; all-digital PLL; cascaded hybrid PLL fabrication; charge-pump PLL; frequency 10 MHz to 315 MHz; jitter; multiplication factor; phase selectable divider; piecewise linear calibrated hierarchical TDC; power 17 mW; relative phase difference; size 65 nm; time-to-digital converter; CMOS process; Clocks; Frequency conversion; Jitter; Nonlinear filters; Phase locked loops; Piecewise linear techniques;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2009. CICC '09. IEEE

Conference_Location

San Jose, CA

Print_ISBN

978-1-4244-4071-9

Electronic_ISBN

978-1-4244-4073-3

Type

conf

DOI

10.1109/CICC.2009.5280849

Filename

5280849