SiGe digital frequency dividers with reduced residual phase noise

A new design methodology for achieving very low residual phase noise in SiGe HBT digital frequency dividers is presented. A modified CML D latch design is proposed that enables the latch to draw more current, thereby reducing the residual phase noise. The latch modification yields a 10 dB phase noise improvement over a standard D latch topology, with measurements at 10 GHz resulting in a phase noise floor of - 160 dBc/Hz. The circuit dissipates 350 mW of DC power, but a standard phase noise figure-of-merit that accounts for phase noise, DC power dissipation, and operating frequency, reveals that this new design is among the best in its class.