Title :
A 12-b 56MS/s pipelined ADC in 65nm CMOS
Author :
Leuciuc, A. ; Evans, W. ; Ji, H. ; Naviasky, E. ; He, X.
Author_Institution :
Cadence Design Syst., Columbia, MD, USA
Abstract :
This paper describes a 1.2 V, 12-b pipelined ADC implemented in a 65 nm CMOS process. The circuit design techniques used to obtain high gain operational amplifiers in a deep-submicron process are described. A novel top-level simulation methodology is used to quantify the transient errors in each subrange stage, allowing their optimal design. The circuit employs various techniques for power reduction: class A-B op-amps, improved reference design, and frequency-to-current biasing.
Keywords :
CMOS integrated circuits; analogue-digital conversion; operational amplifiers; CMOS process; circuit design technique; class A-B op-amp; frequency-to-current biasing; operational amplifier; pipelined ADC; size 65 nm; transient error; voltage 1.2 V; CMOS process; Circuit simulation; Circuit synthesis; Frequency; Operational amplifiers;
Conference_Titel :
Custom Integrated Circuits Conference, 2009. CICC '09. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-4071-9
Electronic_ISBN :
978-1-4244-4073-3
DOI :
10.1109/CICC.2009.5280856
