Title :
Low-power design for real-time image segmentation LSI and compact digital CMOS implementation
Author :
Kiriyama, O. ; Morimoto, Takuya ; Adachi, Hidekazu ; Harada, Yournei ; Koide, Tetsushi ; Mattausch, Hans Jurgen
Author_Institution :
Res. Center for Nanodevices & Syst., Hiroshima Univ., Japan
Abstract :
We present a low-power design for real-time digital image segmentation LSI. We design the CMOS test-chip in a 0.35 μm 2-Poly 3-Metal CMOS technology, based on a boundary active only architecture. The design area for 41 × 31 pixels is 51.1mm2 and the integration density is 26.5pixel/mm2. From the circuit simulations at 3.3V supply voltage and 10MHz clock frequency, we obtain a power dissipation of 21.8mW and an image segmentation time of 23μsec.
Keywords :
CMOS digital integrated circuits; VLSI; circuit simulation; image processing equipment; image segmentation; integrated circuit design; low-power electronics; 21.8 mW; 3.3 V; CMOS test-chip; VLSI chip; boundary active only architecture; cell-network construction; circuit simulation; color images; compact digital CMOS implementation; low-power design; real-time image segmentation LSI; region growing approach; CMOS technology; Circuit simulation; Circuit testing; Clocks; Digital images; Frequency; Image segmentation; Large scale integration; Power dissipation; Voltage;
Conference_Titel :
Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on
Print_ISBN :
0-7803-8637-X
DOI :
10.1109/APASIC.2004.1349524
