Design and optimization of CMOS current mode logic dividers

Author

Shinmyo, Akinori ; Hashimoto, Masanori ; Onodera, Hidetoshi

Author_Institution

Dept. Commun. & Comput. Eng., Kyoto Univ., Japan

fYear

2004

Firstpage

434

Lastpage

435

Abstract

We designed and measured a high-speed CML divider in a 0.18 μm CMOS process. The fabricated chip operates at up to 10GHz with power consumption of 8.6mW. From a small-signal equivalent circuit model, we derive an analytical performance model that gives the relationship among maximum operation frequency, gate width and load resistance. We also discuss the design optimization based on the derived performance model.

Keywords

CMOS logic circuits; circuit optimisation; current-mode circuits; current-mode logic; equivalent circuits; flip-flops; frequency dividers; high-speed integrated circuits; integrated circuit design; integrated circuit modelling; low-power electronics; 8.6 mW; CML D-latches; CMOS current mode logic dividers; circuit topology; design optimization; divider design; gate width; high-speed CML divider; load resistance; maximum operation frequency; performance model; small-signal equivalent circuit model; CMOS logic circuits; CMOS process; Design optimization; Electrical resistance measurement; Energy consumption; Equivalent circuits; Logic design; Performance analysis; Semiconductor device measurement; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-8637-X

Type

conf

DOI

10.1109/APASIC.2004.1349525

Filename

1349525