A continuous-time input pipeline ADC with inherent anti-alias filtering

The first continuous-time input pipeline Nyquist rate ADC architecture with inherent anti-alias filtering is introduced. Such an approach overcomes many of the challenges associated with a pure switched-capacitor architecture. Inherent anti-alias filtering is implemented in the first stage MDAC using first order Sinc filtering and a simple RC filter, allowing the possibility of eliminating costly anti-alias filters. The effect of switched-capacitor sampling distortion is reduced. This architecture also eases the jitter requirements of the ADC clock when compared to switched capacitor pipeline ADCs. 9.85 ENOB is achieved with 21.4 mW analog power from a 1.8 V supply at 26 MSPS in a 0.18 mum CMOS process.