Title :
A 1-GS/s 6-bit 6.7-mW ADC in 65-nm CMOS
Author :
Yang, Jing ; Naing, Thura Lin ; Brodersen, Bob
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Berkeley Wireless Res. Center, Berkeley, CA, USA
Abstract :
An asynchronous 6 bit 1 GS/s ADC is achieved by time interleaving two ADCs based on binary successive approximation algorithm (SA) using a capacitive ladder. The semi-close loop asynchronous technique eliminates the high internal clocks and significantly speeds up the SA algorithm. One bit redundancy is implemented to compensate the process variation of parasitic and the MOM capacitance. Fabricated in 65 nm CMOS with an active area of 0.11 mm2, it achieves a peak SNDR of 31.5 dB at 1 GS/s sampling rate and has a power consumption of 6.7 mW for the analog and digital processing.
Keywords :
CMOS logic circuits; analogue-digital conversion; approximation theory; ADC; CMOS process; MOM capacitance; analog processing; asynchronous logic circuits; binary successive approximation algorithm; capacitive ladder; digital processing; power 6.7 mW; power consumption; sampling rate; semiclose loop asynchronous technique; size 65 nm; Approximation algorithms; CMOS process; Clocks; Energy consumption; Interleaved codes; Message-oriented middleware; Parasitic capacitance; Sampling methods; Analog-to-digital conversion; asynchronous logic circuits; binary successive approximation algorithm; cognitive radios; semi-close loop; time-interleaving;
Conference_Titel :
Custom Integrated Circuits Conference, 2009. CICC '09. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-4071-9
Electronic_ISBN :
978-1-4244-4073-3
DOI :
10.1109/CICC.2009.5280861
