Title :
Energy-performance tunable logic
Author :
Nezamfar, Bita ; Horowitz, Mark
Author_Institution :
Stanford Univ., Stanford, CA, USA
Abstract :
An externally static, internally dynamic topology creates a new logic family that enables the user to tune effective transistor thresholds post-fabrication by adjusting a few power supplies. These gates can therefore be programmed for higher speed or for lower power based on the system requirements. An application of this logic to programmable interconnect circuits is shown in this paper. In a 90-nm test chip, the circuit achieves the same performance as conventional static circuits at 65% energy and has a 2X wider energy-performance tuning range. This property enables building in-field energy-performance tunable FPGAs.
Keywords :
field programmable gate arrays; logic gates; logic testing; field programmable gate arrays; internally dynamic topology; logic family; logic gates; programmable interconnect circuits; size 90 nm; transistor thresholds; Circuit optimization; Circuit testing; Circuit topology; Field programmable gate arrays; Integrated circuit interconnections; Logic circuits; Power supplies; Power system interconnection; Tunable circuits and devices;
Conference_Titel :
Custom Integrated Circuits Conference, 2009. CICC '09. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-4071-9
Electronic_ISBN :
978-1-4244-4073-3
DOI :
10.1109/CICC.2009.5280874
