A novel high speed MCML square root carry select adder for mixed-signal applications

This paper presents a MOS current mode logic (MCML) square root carry select adder (SQ-CSA) which can be used as an alternative to MCML ripple carry adder (RCA) when the number of bits in the input words is large. The proposed 16-bit MCML SQ-CSA has been implemented and simulated in PSPICE using TSMC 180 nm CMOS technology parameters. Its performance has been compared with 16-bit RCAs based on CMOS and MCML styles and 16-bit CMOS SQ-CSA. It is found that the proposed 16-bit MCML SQ-CSA reduces the worst case delay by 67.50% and 72.49% in comparison to the MCML and CMOS based RCAs respectively. Also, the proposed 16-bit MCML SQ-CSA adder results in 26.55% reduction in delay in comparison to CMOS SQ-CSA. In terms of power consumption, the proposed MCML SQ-CSA shows a reduction of 58.97% in comparison to CMOS SQ-CSA.