Title :
High speed CMOS multiplier using CVTL technique
Author_Institution :
Dept. of Comput. Sci. & Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Abstract :
A high speed CMOS multiplier using critical voltage transition logic (CVTL) technique is presented. The gate outputs are preconditioned to minimize gate delay using a new clocking scheme and circuit design. The simulated CMOS 4×4 multiplier circuit shows that the average speed improvement of the new circuit is two times better than that of static implementations in the 0.35 μm process. The simulation results also show that the new circuit can achieve smaller delay-power product compared to that of its static counterpart.
Keywords :
CMOS logic circuits; clocks; minimisation; 0.35 micron; CMOS 4×4 multiplier circuit; CVTL technique; circuit design; clocking scheme; critical voltage transition logic; delay-power product; gate delay minimization; gate output preconditioning; high speed CMOS multiplier; Adders; CMOS logic circuits; CMOS process; Circuit synthesis; Delay; Logic arrays; Logic circuits; Logic design; Logic gates; Voltage;
Conference_Titel :
Communications, Circuits and Systems, 2005. Proceedings. 2005 International Conference on
Print_ISBN :
0-7803-9015-6
DOI :
10.1109/ICCCAS.2005.1495290
