A sub-2W 39.8-to-44.6Gb/s transmitter and receiver chipset with SFI-5.2 interface in 40nm CMOS

Author

Raghavan, Bharath ; Delong Cui ; Singh, Upendra ; Maarefi, H. ; Pi, D. ; Vasani, A. ; Zhi Huang ; Momtaz, Afshin ; Jun Cao

Author_Institution

Broadcom, Irvine, CA, USA

fYear

2013

Firstpage

32

Lastpage

33

Abstract

The introduction of 40Gb/s networks, spurred by 40Gb/s WDM growth, can alleviate bandwidth bottlenecks of Internet infrastructure while simultaneously reducing operating costs. Increasingly, standard CMOS technology is used to enable transceiver speeds [1-5] previously achievable only by using expensive bipolar technology. However, at 40Gb/s, limited channel bandwidth coupled with stringent receiver jitter tolerance requirements demands better solutions than exist currently.

Keywords

CMOS integrated circuits; Internet; jitter; radio receivers; radio transmitters; wavelength division multiplexing; CMOS technology; Internet infrastructure; SFI-5.2 interface; WDM; bit rate 39.8 Gbit/s to 44.6 Gbit/s; power 0 W; receiver chipset; receiver jitter tolerance; size 40 nm; transmitter chipset; wavelength division multiplexing; Bandwidth; CMOS integrated circuits; Clocks; Jitter; Phase locked loops; Receivers; Semiconductor device measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-4673-4515-6

Type

conf

DOI

10.1109/ISSCC.2013.6487624

Filename

6487624