Title :
Analog DLL-based period synthesis circuit
Author :
Kwasniewski, T.A.
Abstract :
An indirect analog period synthesis circuit, which can generate a target period from a reference period, is presented. It uses analog switches and an analog delay-locked loop (DLL) to generate a fractional ratio of the input clock. This circuit has been implemented in 0.18 μm CMOS technology using 200 MHz input reference frequency. It can generate the desired period with an acceptable resolution of around 1% and switch from one target period to another in less than 2 μs.
Keywords :
CMOS analogue integrated circuits; clocks; delay lock loops; switches; 0.18 micron; 200 MHz; CMOS technology; analog DLL; analog delay-locked loop; analog switches; fractional ratio; input clock; period synthesis circuit; CMOS technology; Circuit synthesis; Clocks; Communication switching; Delay effects; Delay lines; Frequency; Signal synthesis; Switches; Synthesizers;
Conference_Titel :
Communications, Circuits and Systems, 2005. Proceedings. 2005 International Conference on
Print_ISBN :
0-7803-9015-6
DOI :
10.1109/ICCCAS.2005.1495296
