Architectural VHDL design and test synthesis

The effect of high level VHDL synthesis, combined with VHDL simulation, is to greatly improve engineering productivity, product quality, and shorten time to market. As ASIC and system complexity approaches 50000 gates, traditional approaches of schematic and RTL descriptions cannot keep pace with the design complexity-the design becomes unmanageable and the designer gets lost in a sea of gates. With the advent of high level behavioural synthesis the designer creates a compact representation of the design without having to generate the the low (RTL or gate) level descriptions manually. This paper discusses the practical requirements of maintaining control over the cost of test, through the use of test synthesis