Design for testability in highly integrated ASIC solutions

When designing complex ASICs, the methodology for testing the device and the system must be considered at the onset of the design process. A design for test strategy should be part of the design specification to ensure that it follows through the complete design cycle. This paper outlines the approach used in several complex digital ASIC developments and how this design for test approach has been implemented. The authors will discuss the implementation of the IEEE1149.1 Boundary Scan standards in these devices. Use of the boundary scan circuitry for PCB test is also discussed. The addition of BITE structures allows in-system monitoring of the devices to ensure they are operating correctly and to reset them if they come out of synchronisation with the rest of the system. This approach along with full scan logic, ATPG and BIST structures where applicable lead to a design which has a high level of test