Title :
A 1-mW 12-Gb/s continuous-time adaptive passive equalizer in 90-nm CMOS
Author :
Shin, Dong Hun ; Jang, Ji Eun ; Mahony, Frank O. ; Yue, C. Patrick
Author_Institution :
High-Speed Silicon Lab., Univ. of California, Santa Barbara, CA, USA
Abstract :
This paper presents a frequency-domain adaptive passive equalizer for high-speed receivers. A local control loop, without feedback from the final receiver output, is used to automatically adjust the gain compensation for different channel characteristics. As a result, the equalizer does not rely on the recovered clock signal. Implemented in a 90-nm digital CMOS process, the equalizer can provide up to 13 dB of gain compensation with 6 dB of tuning range while consuming 1 mW from a 1-V supply. The equalizer is able to open the data eye of a 12-Gb/s PRBS signal after a 72-inch RG-58 coaxial cable and an 8-inch FR-4 trace, whose attenuations at 6 GHz are 10.8 and 13 dB, respectively.
Keywords :
CMOS digital integrated circuits; adaptive equalisers; high-speed integrated circuits; receivers; FR-4 trace; PRBS signal; RG-58 coaxial cable; bit rate 12 Gbit/s; continuous-time adaptive passive equalizer; frequency 6 GHz; frequency-domain adaptive passive equalizer; gain compensation; high-speed receivers; local control loop; power 1 mW; recovered clock signal; size 72 inch; size 8 inch; size 90 nm; voltage 1 V; Attenuation; Automatic control; CMOS process; Clocks; Coaxial cables; Equalizers; Feedback loop; Gain; Output feedback;
Conference_Titel :
Custom Integrated Circuits Conference, 2009. CICC '09. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-4071-9
Electronic_ISBN :
978-1-4244-4073-3
DOI :
10.1109/CICC.2009.5280898
