Multi-level logic synthesis for Concurrent Logic CLi6000 devices

Concurrent Logic CLi6000 devices are high granularity, RAM-based reconfigurable FPGAs. The architecture consists of a grid of small cells surrounded by programmable input/output blocks and programmable interconnect. This paper proposes a logic synthesis procedure for complex designs. A register transfer level description of the design can be optimized using multi-level synthesis techniques and then mapped to the FPGA