Comparing several implementations of a hardware hasher unit

As part of the design of a knowledge-base server, there arose a requirement for a hardware sub-unit which could perform a general hashing function on variable length tuples. The knowledge-base server uses transputers for its internal control. The hardware hasher unit replaces an OCCAM procedure which took an unacceptably long time to execute (about 10 microseconds). The target time was under 160 nanoseconds. The first implementation of the hardware hasher was carried out using conventional GAL technology. This worked at acceptable speed (order of 40 nanoseconds) but the nine GAL chips took up a relatively large amount of PCB area. Hasher designs have since been implemented in Xilinx 3000 series FPGA technology, Altera MAX series 5000 technology, Actel ACT1 technology, National MAPL technology, AMD MACH technology, and Lattice Semiconductor pLSI technology. This paper compares the speed, cost and PCB area for all seven designs. The authors also comment generally on the suitability of each candidate technology for this type of task, and then draw some conclusions which may help to guide future designs in other applications areas