Algorithm and architecture for high speed merged arithmetic FIR filter generation

This paper presents a new method and an algorithm for the synthesis of a high-speed variable coefficients Finite Impulse Response (FIR) filter. Timing performance and reduced area are achieved employing two techniques. Firstly, a merged arithmetic architecture is used to synthesize the FIR filter function directly. Secondly, an algorithm that looks for minimum delay Partial Product Reduction Tree (PPRT) is developed. These results are combined to create a program that furnishes a speed optimized netlist for the filter. The performance of the proposed method has been evaluated by comparing it to the result achieved by cell-based synthesis software.