Title :
Design optimizations for reduced power and higher operating frequency in a custom x86-64 processor core
Author :
Keshlear, W. ; Oliver, S. ; Colyer, R. ; Schreiber, J. ; Antoniadis, T. ; Mickelson, T. ; Puzey, T. ; Bates, M.
Author_Institution :
Central Eng., Adv. Micro Devices, Inc., Austin, TX, USA
Abstract :
This paper describes the methodology and tools used to drive static and dynamic power savings while significantly improving the operating frequency of a 45 nm custom x86-64 processor core used in several multi-core devices. The power improvements were essential for future six-, eight-, and twelve-core server processors, but notable improvements have already been observed in the four-core, 2.7-GHz server product and the four-core, 3.0-GHz client product.
Keywords :
VLSI; circuit optimisation; integrated circuit design; low-power electronics; microprocessor chips; circuit optimization; client product; custom x86-64 processor core design optimisation; dynamic power reduction; dynamic power savings; frequency 2.7 GHz; frequency 3.0 GHz; integrated circuit design; microprocessor; multicore device; server product; size 45 nm; static power reduction; very-large-scale integration; Design optimization; Frequency; circuit optimization; integrated circuit design; microprocessors; optimization methods; very-large-scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 2009. CICC '09. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-4071-9
Electronic_ISBN :
978-1-4244-4073-3
DOI :
10.1109/CICC.2009.5280915
