Title :
A 200mW 100MHz-to-4GHz 11th-order complex analog memory polynomial predistorter for wireless infrastructure RF amplifiers
Author_Institution :
Scintera, Sunnyvale, CA, USA
Abstract :
The trend toward heterogeneous networks encompassing legacy high-power base stations (macro-BTS) with lightweight and easy to deploy small cells calls for inexpensive and efficient Power Amplifier (PA) linearizers. Current macro-BTSs relying on Digital Predistortion Techniques (DPD) are too power hungry and costly to be used in small cells. In this paper, we present a fully integrated, 11th-order, 4-memory term, temperature-compensated complex analog polynomial predistorter. It is implemented in 0.18μm CMOS, does not require calibration and offers up to 25dB linearity improvement. Several integrated [1,2] and discrete [3,4] implementations of Analog Predistorters (APD) have been published. This paper reports a complex high-order predistorter integrating the RF and the IF on the same die (RFPD).
Keywords :
CMOS analogue integrated circuits; MMIC power amplifiers; field effect MMIC; polynomials; CMOS process; PA linearizers; digital predistortion techniques; eleven-order complex analog memory polynomial predistorter; frequency 100 MHz to 4 GHz; heterogeneous networks; high-power base stations; macroBTS; power 200 mW; power amplifier linearizers; size 0.18 mum; temperature-compensated complex analog polynomial predistorter; wireless infrastructure RF amplifiers; CMOS integrated circuits; Peak to average power ratio; Polynomials; Predistortion; Radio frequency; Wireless communication;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-4515-6
DOI :
10.1109/ISSCC.2013.6487652
