A congestion driven re-synthesis method after floorplanning

Routing congestion is a major concern in the IC design flow. This paper presents a novel congestion driven high-level re-synthesis method after floorplanning. The objective of this method is to distribute the routing demands most evenly on the chip in the early design phase before physical design begins. By doing this, it is less likely for local congestion area to occur in the subsequent physical design stage and it is much easier for physical design to solve congestion even it occurs. Our algorithm estimates the distribution of the routing demands from the physical information generated by floorplanning. Then, by high-level re-scheduling and re-allocating, it reforms the topological interconnect relations between modules to optimize the routing demands distribution. This algorithm is simulated annealing based. We have conducted experiment on some public available test benches. Experimental results show that compared with original circuits, 40% reduction of the maximal routing demands and about 60% reduction of the amount of global edges with high routing demands is performed by our method.