DocumentCode
1704713
Title
Time to digital converter based on a 2-dimensions Vernier architecture
Author
Liscidini, Antonio ; Vercesi, Luca ; Castello, Rinaldo
Author_Institution
Univ. of Pavia, Pavia, Italy
fYear
2009
Firstpage
45
Lastpage
48
Abstract
A novel 2-dimension Vernier Time to digital converter (TDC) is presented. The proposed architecture reduces drastically the number of delay stage required by linear TDCs minimizing the power consumption and the area of the design. A 7 bits TDC prototype realized in 65 nm CMOS technology is presented. The chip has a resolution of 4.8 ps with a power consumption of 1.7 mW at a conversion rate of 50 Msps.
Keywords
convertors; integrated circuit design; 2D Vernier architecture; CMOS technology; delay stage; digital converter; power 1.7 mW; power consumption; size 65 nm; time 4.8 ps; word length 7 bit; CMOS technology; Delay; Energy consumption; Prototypes;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2009. CICC '09. IEEE
Conference_Location
San Jose, CA
Print_ISBN
978-1-4244-4071-9
Electronic_ISBN
978-1-4244-4073-3
Type
conf
DOI
10.1109/CICC.2009.5280922
Filename
5280922
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