• DocumentCode
    1704736
  • Title

    On embeddings of neural networks into massively parallel computer systems

  • Author

    Cong, Bin

  • Author_Institution
    Dept. of Comput. Sci., South Dakota State Univ., Brookings, SD, USA
  • Volume
    1
  • fYear
    1997
  • Firstpage
    231
  • Abstract
    Artificial neural networks (ANNs) have many characteristics that are suitable for massively parallel computation: simple processing units (neurons), small local memory requirement for each neuron, highly parallel operations. Naturally, neural network implementation should be a target for massively parallel computing. This paper presents and discusses techniques to map a neural network algorithm onto a massively parallel computer system. The goal is to maximize parallelism by breaking the ANN computation into basic units and processing these units in parallel. The following strategies are discussed: (1) design special highly parallel computers for artificial neural networks; (2) map the neural network algorithms directly onto the existing general-purpose parallel computers; (3) map the neural network algorithms onto the optical bus based systems; (4) design new structured neural networks that are similar to the topologies of the existing parallel systems; (5) use the divide-and-conquer technique to break a large neural network into many small ones, each will be processed by a PC or workstation
  • Keywords
    backpropagation; network topology; neural net architecture; parallel architectures; pipeline processing; ANN; PC; algorithmic mapping; artificial neural networks; divide-and-conquer technique; embeddings; general-purpose parallel computers; highly parallel computers; local memory requirement; massively parallel computer systems; neural network algorithms; neural networks; neurons; optical bus; structured neural networks; workstation; Algorithm design and analysis; Artificial neural networks; Computer networks; Concurrent computing; Embedded computing; Neural networks; Neurons; Optical computing; Optical design; Parallel processing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Aerospace and Electronics Conference, 1997. NAECON 1997., Proceedings of the IEEE 1997 National
  • Conference_Location
    Dayton, OH
  • Print_ISBN
    0-7803-3725-5
  • Type

    conf

  • DOI
    10.1109/NAECON.1997.618084
  • Filename
    618084