DocumentCode
1704792
Title
A sub-2.5ns frequency-hopped quadrature frequency synthesizer in 0.13-μm technology
Author
Lanka, Narasimha ; Patnaik, Satwik ; Harjani, Ramesh
Author_Institution
Univ. of Minnesota, Minneapolis, MN, USA
fYear
2009
Firstpage
57
Lastpage
60
Abstract
This paper presents a fast-hopping frequency synthesizer architecture with quadrature outputs, based on sub-harmonic injection-locking, that is compliant with Wireless-USB/WiMedia specifications. The synthesizer features a cross-coupled quadrature digitally-controlled oscillator, that is injection locked to a sub-harmonic frequency. On-chip mixers have been implemented to measure the quadrature accuracy of the outputs. The overall architecture is a CMOS-only implementation and has been fabricated in 0.13-mum SiGe BiCMOS process. Measurement results indicate lock-times of less than 2.5 ns, a locked phase noise of -114 dBc/Hz at 1 MHz offset and a quadrature accuracy of better than 0.5deg. The frequency synthesizer (excluding output buffers) occupies an area of 0.27 mm2 and consumes 14.5 mW of power. The best and worst case spur suppression achieved are 47 and 31 dB, respectively. This is the lowest power fast-hopping quadrature frequency synthesizer that has been reported to date.
Keywords
BiCMOS integrated circuits; Ge-Si alloys; frequency synthesizers; mixers (circuits); oscillators; BiCMOS process; SiGe; WiMedia; Wireless-USB; frequency-hopped quadrature frequency synthesizer; on-chip mixers; power 14.5 mW; quadrature digitally-controlled oscillator; size 0.13 mum; sub-harmonic injection-locking; BiCMOS integrated circuits; Frequency synthesizers; Germanium silicon alloys; Injection-locked oscillators; Noise measurement; Phase measurement; Phase noise; Silicon germanium;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2009. CICC '09. IEEE
Conference_Location
San Jose, CA
Print_ISBN
978-1-4244-4071-9
Electronic_ISBN
978-1-4244-4073-3
Type
conf
DOI
10.1109/CICC.2009.5280925
Filename
5280925
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