Title :
100Gb/s ethernet chipsets in 65nm CMOS technology
Author :
Jhih-Yu Jiang ; Ping-Chuan Chiang ; Hao-Wei Hung ; Chen-Lun Lin ; Ty Yoon ; Jri Lee
Author_Institution :
Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
This paper presents a complete design of 100GbE chipsets including gearbox TX/RX, LDD and TIA/LA arrays. Figure 7.3.1 shows the architecture, where 10×10Gb/s input data is serialized into 4×25Gb/s bit stream by a 10:4 serializer (i.e., gearbox TX). A 4-element LDD array subsequently drives 4 laser diodes, emitting 850nm light into 4 multimode fibers (MMFs). After traveling over 100m, these optical signals are captured and transformed into electrical domain by means of photo diodes (PDs) and a TIA/LA array. A 4:10 deserializer (gear-box RX) recovers the clock and data, and restores the data sequences into 10×10Gb/s outputs. In applications, gearbox TRX and optical frontends (i.e., LDD and TIA/LA arrays) may be separated by several inches in order to fulfill system-level integration.
Keywords :
CMOS integrated circuits; integrated optoelectronics; optical fibre LAN; photodiodes; 10:4 serializer; 4-element LDD array; 4:10 deserializer; CMOS technology; Ethernet chipsets; MMF; TIA-LA arrays; bit rate 100 Gbit/s; data sequences; gearbox TRX; laser diodes; multimode fibers; optical frontends; optical signals; photodiodes; system-level integration; wavelength 850 nm; Arrays; CMOS integrated circuits; Clocks; Optical feedback; Optical fibers; Vertical cavity surface emitting lasers;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-4515-6
DOI :
10.1109/ISSCC.2013.6487663
