Title :
Monolithic IC of SDH STM-16 optical receiver, core circuits
Author :
Yingmei, Chen ; Zhigong, Wang ; Li Zhang ; Mingzheng, Xiong
Author_Institution :
Inst. of RF&OE-ICs, Southeast Univ., Nanjing, China
Abstract :
The design and the experimental results of a monolithic packed IC with functions of clock recovery, data decision and 1:4 demultiplexer for 2.5-Gb/s fiber-optic communications have been provided. The IC was implemented in TSMC 0.25μm CMOS process. The capture range of the PLL is 80-MHz, the recovered and frequency divided 625-MHz clock has a phase noise of -106.26dBc/Hz at 100-kHz offset in response to 2.5-Gb/s PRBS input data (231-1), and the 2.5-Gb/s PRBS data have been demultiplexed to four 625-Mb/s data.
Keywords :
CMOS integrated circuits; demultiplexing; integrated circuit design; integrated circuit measurement; integrated circuit noise; optical fibre communication; optical receivers; phase locked loops; phase noise; synchronisation; telecommunication equipment testing; 2.5 Gbit/s; 625 MHz; 625 Mbit/s; PLL capture range; PRBS input data; SDH STM-16 optical receiver; TSMC CMOS process; clock recovery; core circuits; data decision; demultiplexer; design; fiber-optic communications; frequency offset; monolithic IC; monolithic packed IC; phase noise; recovered frequency divided clock; CMOS integrated circuits; CMOS process; Clocks; Frequency conversion; Monolithic integrated circuits; Optical fiber communication; Optical receivers; Phase locked loops; Photonic integrated circuits; Synchronous digital hierarchy;
Conference_Titel :
Communications, Circuits and Systems, 2005. Proceedings. 2005 International Conference on
Print_ISBN :
0-7803-9015-6
DOI :
10.1109/ICCCAS.2005.1495342
